This invention is in the field of solid-state memory as realized in semiconductor integrated circuits. Embodiments of this invention are more specifically directed to the operation of data paths in such memories in read and write access operations.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now portable or handheld devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, and the like. An important class of mobile devices are implantable medical devices, such as pacemakers, defibrillators, and the like. In each of these cases, these systems and devices must be battery powered to in fact be mobile. The power consumption of the electronic circuitry in those devices and systems is therefore of great concern, as battery life is often a significant factor in the buying decision as well as in the utility of the device or system.
Many mobile devices, including implantable medical devices, now rely on solid-state memory not only for data storage during operation, but also as non-volatile memory for storing program instructions (e.g., firmware) and for storing the results and history of previous operations and calculations. Electrically-erasable programmable read-only memory (EEPROM) is a common type of solid-state non-volatile memory, particularly EEPROM of the “flash” type. Ferroelectric random-access memory (FeRAM) is a popular non-volatile solid-state memory technology, particularly in implantable medical devices. Modern mobile devices typically include substantial non-volatile memory capacity, often amounting to as much as one or more gigabytes.
As mentioned above, power consumption of integrated circuit functions is an important concern in the design and manufacture of mobile electronic devices and systems. The miniaturization of these integrated circuit functions is also an important design goal, whether to minimize manufacturing cost or to provide a minimum form factor. Given the substantial memory capacity now required by these computationally sophisticated, the chip area involved in realizing solid-state memory, particularly non-volatile solid-state memory is a large portion of the overall chip area.
According to conventional techniques, one approach to reducing chip area in solid-state memory, particularly non-volatile memory such as FeRAM, is to time-multiplex the communication of data words along internal buses. As known in the art, “page mode” access involves the accessing of a row of memory cells, from which successive data elements (e.g., bytes) can be rapidly retrieved or written. Page-mode access enables error-correction coding (ECC) to be applied over the row as a whole, rather than on a byte-by-byte basis, resulting in fewer additional memory cells for storing the ECC code bits to achieve a given level of error correction. For example, ECC can be performed using six code bits over four payload bytes (a data word of thirty-two payload bits) rather than four code bits per byte, which requires fewer code bits (six bits vs. sixteen bits for each data word) in the memory. The chip area for implementing this page mode and row-wide ECC approach can be reduced by time-multiplexing the data communications on using an internal data bus that is narrower than the number of bits in the accessed row. If six code bits are used for a four-byte payload, the entire row is thirty-eight bits wide; 2× internal multiplexing would reduce the internal bus width from thirty-eight conductors to nineteen conductors (for differential signals, from seventy-six to thirty-eight conductors), reducing the chip area requirements by one-half for this internal bus. In some memories, multiple “segments” of the array are accessed by way of the internal bus, in which case the reduction in chip area is especially substantial.
However, as mentioned above, power consumption by the memory is also of great concern in these solid-state memories, particularly if implemented in mobile or implantable devices and systems. In the context of the time-multiplexed internal bus, the chip area savings comes at a cost of increased switching rates on the internal bus, such increased switching rates reflected in increased power consumption by the memory function itself.